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ICDE
2010
IEEE
248views Database» more  ICDE 2010»
16 years 1 months ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
Gustavo Alonso, Jens Teubner, René Mül...
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
15 years 8 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
15 years 8 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
15 years 7 months ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
3DPVT
2006
IEEE
199views Visualization» more  3DPVT 2006»
15 years 8 months ago
Fast Level Set Multi-View Stereo on Graphics Hardware
In this paper, we show the importance and feasibility of much faster multi-view stereo reconstruction algorithms relying almost exclusively on graphics hardware. Reconstruction al...
Patrick Labatut, Renaud Keriven, Jean-Philippe Pon...