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CHES
2009
Springer
162views Cryptology» more  CHES 2009»
15 years 10 months ago
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Abstract. This paper is devoted to the design of fast parallel accelerators for the cryptographic Tate pairing in characteristic three over supersingular elliptic curves. We propos...
Jean-Luc Beuchat, Jérémie Detrey, Ni...
76
Voted
DATE
2005
IEEE
98views Hardware» more  DATE 2005»
15 years 3 months ago
Hardware Accelerated Power Estimation
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the ob...
Joel Coburn, Srivaths Ravi, Anand Raghunathan
DATE
2005
IEEE
168views Hardware» more  DATE 2005»
15 years 3 months ago
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
81
Voted
SI3D
2006
ACM
15 years 3 months ago
Hardware accelerated multi-resolution geometry synthesis
In this paper, we propose a new technique for hardware accelerated multi-resolution geometry synthesis. The level of detail for a given viewpoint is created on-the-fly, allowing f...
Martin Bokeloh, Michael Wand
71
Voted
ASAP
2007
IEEE
122views Hardware» more  ASAP 2007»
15 years 3 months ago
Parallelizing HMMER for Hardware Acceleration on FPGAs
Profile based Hidden Markov Model is a widely used tool in bioinformatics. While being very valuable to biologists, it is extremely compute intensive and suffers from prohibitive...
Steven Derrien, Patrice Quinton