As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...
The Hamiltonian Cycle (HC) problem is an important graph problem with many applications. The general backtracking algorithm normally used for random graphs often takes far too lon...
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...