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ISCAS
2002
IEEE
111views Hardware» more  ISCAS 2002»
15 years 8 months ago
CASCADE - configurable and scalable DSP environment
As the complexity of embedded systems grows rapidly, it is common to accelerate critical tasks with hardware. Designers usually use off-the-shelf components or licensed IP cores t...
Tay-Jyi Lin, Chein-Wei Jen
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 9 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
ASAP
2006
IEEE
121views Hardware» more  ASAP 2006»
15 years 7 months ago
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...
Humberto Calderon, Stamatis Vassiliadis
ISCAS
2003
IEEE
116views Hardware» more  ISCAS 2003»
15 years 8 months ago
Using FPGAs to solve the Hamiltonian cycle problem
The Hamiltonian Cycle (HC) problem is an important graph problem with many applications. The general backtracking algorithm normally used for random graphs often takes far too lon...
Micaela Serra, Kenneth B. Kent
ASPDAC
2005
ACM
79views Hardware» more  ASPDAC 2005»
15 years 5 months ago
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks
Abstract— This paper presents an optimized channel usage between simulator and accelerator when the simulator models transaction-level SoC while accelerator models RTL sub-blocks...
Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-...