In this poster, we present how our previously published method of computing continuous 2D scatterplots can be performed with hardware acceleration on a GPU. By doing this, we expl...
We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in columnwise processing with...
Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmi...
The reconfigurable mesh is a model for massively parallel computing for which many algorithms with very low complexity have been developed. These algorithms execute cycles of bus...
This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a...
Renate Henftling, Andreas Zinn, Matthias Bauer, Wo...
— We propose a methodology for Boolean matching under permutations of inputs and outputs (PP-equivalence checking problem) — a key step in incremental logic design that identif...