308 search results - page 22 / 62 » Macromodeling of analog circuits for hierarchical circuit de... |
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
This paper demonstrates a system that performs multiobjective sizing across 100,000 analog circuit topologies simultaneously, with SPICE accuracy. It builds on a previous system, ...
44
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ICCD
2007
IEEE
15 years 4 months ago
2007
IEEE
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
107
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DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose ...
ASPDAC
2005
ACM
15 years 3 months ago
2005
ACM
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...