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DATE
2005
IEEE
120views Hardware» more  DATE 2005»
15 years 3 months ago
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
This paper reports a novel simulation methodology for analysis and prediction of substrate noise impact on analog / RF circuits taking into account the role of the parasitic resis...
Charlotte Soens, Geert Van der Plas, Piet Wambacq,...
ISCAS
2003
IEEE
134views Hardware» more  ISCAS 2003»
15 years 6 months ago
Analog and mixed signal modelling with SystemC-AMS
SystemC will become more and more important for the design of digital circuits from the specification down to the RT-Level. Complex systems often contain analog components. This p...
Alain Vachoux, Christoph Grimm, Karsten Einwich
DAC
2006
ACM
16 years 2 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
16 years 1 months ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni
ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
15 years 6 months ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar