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DATE
2003
IEEE
151views Hardware» more  DATE 2003»
15 years 3 months ago
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits
The architectural study of wireless communication systems typically requires simulations with high-level models for different analog and RF blocks. Among these blocks, frequency-t...
Petr Dobrovolný, Gerd Vandersteen, Piet Wam...
GECCO
2000
Springer
150views Optimization» more  GECCO 2000»
15 years 1 months ago
Automatic Synthesis of Electrical Circuits Containing a Free Variable Using Genetic Programming
A mathematical formula containing one or more free variables is "general" in the sense that it represents the solution to all instances of a problem (instead of just the...
John R. Koza, Martin A. Keane, Jessen Yu, William ...
ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
15 years 2 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
ISVLSI
2006
IEEE
115views VLSI» more  ISVLSI 2006»
15 years 3 months ago
The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel
In this paper, the design techniques and considerations for each building block required for analog signal processing in HD-DVD PRML read channel are presented and the procedures ...
Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsi...
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 1 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar