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ESOP
2010
Springer
15 years 9 months ago
Parameterized Memory Models and Concurrent Separation Logic
Formal reasoning about concurrent programs is usually done with the assumption that the underlying memory model is sequentially consistent, i.e. the execution outcome is equivalen...
Rodrigo Ferreira, Xinyu Feng and Zhong Shao
JODL
2000
123views more  JODL 2000»
14 years 11 months ago
On Z39.50 wrapping and description logics
Z39.50 is a client/server protocol widely used in digital libraries and museums for searching and retrieving information spread over a number of heterogeneous sources. To overcome ...
Yannis Velegrakis, Vassilis Christophides, Panos C...
BMCBI
2007
109views more  BMCBI 2007»
14 years 12 months ago
A cis-regulatory logic simulator
Background: A major goal of computational studies of gene regulation is to accurately predict the expression of genes based on the cis-regulatory content of their promoters. The d...
Robert D. Zeigler, Jason Gertz, Barak A. Cohen
INTERSPEECH
2010
14 years 6 months ago
Data-dependent evaluator modeling and its application to emotional valence classification from speech
Practical supervised learning scenarios involving subjectively evaluated data have multiple evaluators, each giving their noisy version of the hidden ground truth. Majority logic ...
Kartik Audhkhasi, Shrikanth S. Narayanan
MSE
2005
IEEE
133views Hardware» more  MSE 2005»
15 years 5 months ago
Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided)
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...
R. James Duckworth