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PPOPP
2010
ACM
16 years 1 months ago
Modeling transactional memory workload performance
Transactional memory promises to make parallel programming easier than with fine-grained locking, while performing just as well. This performance claim is not always borne out bec...
Donald E. Porter, Emmett Witchel
96
Voted
ECIR
2009
Springer
16 years 1 months ago
If I Had a Million Queries
As document collections grow larger, the information needs and relevance judgments in a test collection must be well-chosen within a limited budget to give the most reliable and ro...
Ben Carterette, Virgiliu Pavlu, Evangelos Kanoulas...
ICCD
2008
IEEE
121views Hardware» more  ICCD 2008»
16 years 1 months ago
Characterization and design of sequential circuit elements to combat soft error
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
Hamed Abrishami, Safar Hatami, Massoud Pedram
116
Voted
ICCAD
2005
IEEE
110views Hardware» more  ICCAD 2005»
16 years 1 months ago
Performance analysis of carbon nanotube interconnects for VLSI applications
The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this ...
Navin Srivastava, Kaustav Banerjee
ICCAD
2004
IEEE
85views Hardware» more  ICCAD 2004»
16 years 1 months ago
Improving soft-error tolerance of FPGA configuration bits
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykr...