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ICCD
2007
IEEE
195views Hardware» more  ICCD 2007»
15 years 7 months ago
LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
Jugash Chandarlapati, Mainak Chaudhuri
CHES
2004
Springer
216views Cryptology» more  CHES 2004»
15 years 7 months ago
Efficient Countermeasures against RPA, DPA, and SPA
In the execution on a smart card, side channel attacks such as simple power analysis (SPA) and the differential power analysis (DPA) have become serious threat [15]. Side channel a...
Hideyo Mamiya, Atsuko Miyaji, Hiroaki Morimoto
CNSR
2004
IEEE
131views Communications» more  CNSR 2004»
15 years 7 months ago
Fast Flow Classification over Internet
In order to control and manage highly aggregated Internet traffic flows efficiently, we need to be able to categorize flows into distinct classes and to be knowledgeable about the...
A. Oveissian, Kavé Salamatian, Augustin Sou...
CODES
2004
IEEE
15 years 7 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CF
2006
ACM
15 years 7 months ago
The potential of the cell processor for scientific computing
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As...
Samuel Williams, John Shalf, Leonid Oliker, Shoaib...
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