Sciweavers

93 search results - page 16 / 19
» Manpower Scheduling with Time Windows
Sort
View
HPCA
2005
IEEE
15 years 9 months ago
A Small, Fast and Low-Power Register File by Bit-Partitioning
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
Masaaki Kondo, Hiroshi Nakamura
DCOSS
2010
Springer
15 years 2 months ago
Halo: Managing Node Rendezvous in Opportunistic Sensor Networks
One vision of an opportunistic sensor network (OSN) uses sensor access points (SAPs) to assign mobile sensors with sensing tasks submitted by applications that could be running any...
Shane B. Eisenman, Hong Lu, Andrew T. Campbell
CF
2005
ACM
14 years 11 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
OSDI
2008
ACM
15 years 9 months ago
Predicting Computer System Failures Using Support Vector Machines
Mitigating the impact of computer failure is possible if accurate failure predictions are provided. Resources, applications, and services can be scheduled around predicted failure...
Errin W. Fulp, Glenn A. Fink, Jereme N. Haack
ICCS
2003
Springer
15 years 2 months ago
Application Controlled IPC Synchrony - An Event Driven Multithreaded Approach
Interprocess communication (IPC) is an important phenomenon in distributed computing and operating systems. Microkernels of modern operating systems use synchronous IPC semantics f...
Susmit Bagchi, Mads Nygaard