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DDECS
2009
IEEE
95views Hardware» more  DDECS 2009»
15 years 6 months ago
Self-timed full adder designs based on hybrid input encoding
—Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are desc...
Padnamabhan Balasubramanian, D. A. Edwards, C. Bre...
IJCNN
2008
IEEE
15 years 6 months ago
Hybrid learning architecture for unobtrusive infrared tracking support
—The system architecture presented in this paper is designed for helping an aged person to live longer independently in their own home by detecting unusual and potentially hazard...
K. K. Kiran Bhagat, Stefan Wermter, Kevin Burn
ACL
1989
15 years 1 months ago
A Hybrid Approach to Representation in the Janus Natural Language Processor
In BBN's natural language understanding and generation system (Janus), we have used a hybrid approach to representation, employing an intensional logic for the representation...
Ralph M. Weischedel
FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
15 years 5 months ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
CP
2000
Springer
15 years 4 months ago
Linear Formulation of Constraint Programming Models and Hybrid Solvers
Constraint programming offers a variety of modeling objects such as logical and global constraints, that lead to concise and clear models for expressing combinatorial optimization...
Philippe Refalo