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105
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CGO
2004
IEEE
15 years 4 months ago
Single-Dimension Software Pipelining for Multi-Dimensional Loops
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to outer loops. In this paper, we propose a threestep ap...
Hongbo Rong, Zhizhong Tang, Ramaswamy Govindarajan...
108
Voted
FPGA
2006
ACM
117views FPGA» more  FPGA 2006»
15 years 4 months ago
Context-free-grammar based token tagger in reconfigurable devices
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
Young H. Cho, James Moscola, John W. Lockwood
FPL
2006
Springer
158views Hardware» more  FPL 2006»
15 years 4 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...
102
Voted
FPL
2006
Springer
147views Hardware» more  FPL 2006»
15 years 4 months ago
Non-Uniform Random Number Generation Through Piecewise Linear Approximations
This paper presents a hardware architecture for non-uniform random number generation, which allows the generator's distribution to be modified at run-time without reconfigura...
David B. Thomas, Wayne Luk
FPL
2006
Springer
113views Hardware» more  FPL 2006»
15 years 4 months ago
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
Alastair M. Smith, George A. Constantinides, Peter...