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CCECE
2006
IEEE
15 years 5 months ago
FPGA-Based SAT Solver
Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator,...
Mona Safar, M. Watheq El-Kharashi, Ashraf Salem
ISCAS
2002
IEEE
89views Hardware» more  ISCAS 2002»
15 years 4 months ago
On segmented channel routability
We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field progr...
William N. N. Hung, Xiaoyu Song, Alan J. Coppola, ...
CONSTRAINTS
2010
153views more  CONSTRAINTS 2010»
14 years 9 months ago
Philosophy of the MiniZinc challenge
MiniZinc arose as a response to the extended discussion at CP2006 of the need for a standard modelling language for CP. This is a challenging problem, and we believe MiniZinc makes...
Peter J. Stuckey, Ralph Becket, Julien Fischer
ICSE
2008
IEEE-ACM
15 years 12 months ago
FeatureMapper: mapping features to models
Variability modelling with feature models is one key technique for specifying the problem space of Software Product Lines (SPLs). To allow for the automatic derivation of a concre...
Florian Heidenreich, Jan Kopcsek, Christian Wende
AAAI
2006
15 years 1 months ago
Solving MAP Exactly by Searching on Compiled Arithmetic Circuits
The MAP (maximum a posteriori hypothesis) problem in Bayesian networks is to find the most likely states of a set of variables given partial evidence on the complement of that set...
Jinbo Huang, Mark Chavira, Adnan Darwiche