562 search results - page 39 / 113 » Mapping a Fault-Tolerant Distributed Algorithm to Systems on... |
IEEEPACT
2000
IEEE
15 years 2 months ago
2000
IEEE
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
DCC
2010
IEEE
15 years 4 months ago
2010
IEEE
This paper focuses on optimal analog mappings for zero-delay, distributed source-channel coding. The objective is to obtain the optimal vector transformations that map between m-d...
89
Voted
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Networks-on-Chip (NoC), a new SoC paradigm, has been proposed as a solution to mitigate complex on-chip interconnect problems. NoC architecture consists of a collection of IP core...
88
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents a novel architecture for on-chip neural network training using particle swarm optimization (PSO). PSO is an evolutionary optimization algorithm with a growing ...
DATE
2003
IEEE
2003
IEEE
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures
15 years 2 months ago
In this paper, we present an algorithm which automatically maps the IPs onto a generic regular Network on Chip (NoC) architecture and constructs a deadlock-free deterministic rout...