562 search results - page 4 / 113 » Mapping a Fault-Tolerant Distributed Algorithm to Systems on... |
DSN
2005
IEEE
15 years 3 months ago
2005
IEEE
Designing a distributed fault tolerance algorithm requires careful analysis of both fault models and diagnosis strategies. A system will fail if there are too many active faults, ...
ICPP
2000
IEEE
15 years 1 months ago
2000
IEEE
The idle computers on a local area, campus area, or even wide area network represent a significant computational resource--one that is, however, also unreliable, heterogeneous, an...
ASAP
2007
IEEE
14 years 9 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
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HPCA
2007
IEEE
15 years 10 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
ECRTS
2003
IEEE
15 years 2 months ago
2003
IEEE
When time-triggered (TT) systems are to be deployed for large embedded real-time (RT) control systems in cars and airplanes, one way to overcome bandwidth limitations and achieve ...