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» Mapping of performance metrics between IP and ATM
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LCN
2006
IEEE
15 years 3 months ago
Utility-based Packet Scheduler for Wireless Communications
Abstract— Following widespread availability of wireless Internet, a wide range of applications with differing QoS requirements must share the wireless access. The objective of th...
Ana Aguiar, Adam Wolisz, Horst Lederer
JSA
2010
158views more  JSA 2010»
14 years 4 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
15 years 3 months ago
Parallel FFT computation with a CDMA-based network-on-chip
— Fast Fourier transform (FFT) algorithms are used in a wide variety of digital signal processing applications and many of these require high-performance parallel implementations...
Daewook Kim, Manho Kim, Gerald E. Sobelman
IMR
2003
Springer
15 years 3 months ago
An Adaptable Surface Parameterization Method
Parameterizations of triangulated surfaces are used in an increasing number of mesh processing applications for various purposes. Although demands vary, they are often required to...
Patrick Degener, Jan Meseth, Reinhard Klein
FPL
2006
Springer
127views Hardware» more  FPL 2006»
15 years 1 months ago
On-FPGA Communication Architectures and Design Factors
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...