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ICS
1999
Tsinghua U.
15 years 8 months ago
Nonlinear array layouts for hierarchical memory systems
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....
Siddhartha Chatterjee, Vibhor V. Jain, Alvin R. Le...
IPPS
1998
IEEE
15 years 8 months ago
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhile...
111
Voted
CP
2006
Springer
15 years 7 months ago
The ROOTS Constraint
A wide range of counting and occurrence constraints can be specified with just two global primitives: the Range constraint, which computes the range of values used by a sequence of...
Christian Bessière, Emmanuel Hebrard, Brahi...
FPL
2006
Springer
158views Hardware» more  FPL 2006»
15 years 7 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...
NIPS
2007
15 years 5 months ago
Measuring Neural Synchrony by Message Passing
A novel approach to measure the interdependence of two time series is proposed, referred to as “stochastic event synchrony” (SES); it quantifies the alignment of two point pr...
Justin Dauwels, François B. Vialatte, Tomas...