19 search results - page 4 / 4 » March Tests for Word-Oriented Memories |
ITC
2003
IEEE
13 years 11 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
DATE
2006
IEEE
14 years 9 days ago
2006
IEEE
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
VLSID
2001
IEEE
14 years 6 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
ATS
2009
IEEE
13 years 11 months ago
2009
IEEE
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...