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IPPS
2005
IEEE
15 years 3 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
ICS
2004
Tsinghua U.
15 years 3 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
CONCUR
1998
Springer
15 years 2 months ago
Algebraic Techniques for Timed Systems
Performance evaluation is a central issue in the design of complex real-time systems. In this work, we propose an extension of socalled "Max-Plus" algebraic techniques to...
Albert Benveniste, Claude Jard, Stephane Gaubert
CHI
2005
ACM
15 years 10 months ago
The bubble cursor: enhancing target acquisition by dynamic resizing of the cursor's activation area
We present the bubble cursor ? a new target acquisition technique based on area cursors. The bubble cursor improves upon area cursors by dynamically resizing its activation area d...
Tovi Grossman, Ravin Balakrishnan
CN
2010
152views more  CN 2010»
14 years 10 months ago
An environment-aware mobility model for wireless ad hoc network
Simulation is a cost effective, fast and flexible alternative to test-beds or practical deployment for evaluating the characteristics and potential of mobile ad hoc networks. Sinc...
Sabbir Ahmed, Gour C. Karmakar, Joarder Kamruzzama...