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» Massively parallel processing on a chip
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ICCCN
2008
IEEE
15 years 10 months ago
Massively Parallel Anomaly Detection in Online Network Measurement
—Detecting anomalies during the operation of a network is an important aspect of network management and security. Recent development of high-performance embedded processing syste...
Shashank Shanbhag, Tilman Wolf
CF
2010
ACM
15 years 7 months ago
Towards chip-on-chip neuroscience: fast mining of neuronal spike streams using graphics hardware
Computational neuroscience is being revolutionized with the advent of multi-electrode arrays that provide real-time, dynamic perspectives into brain function. Mining neuronal spik...
Yong Cao, Debprakash Patnaik, Sean P. Ponce, Jerem...
IPPS
2003
IEEE
15 years 9 months ago
Architectural Frameworks for MPP Systems on a Chip
Advances in fabrication techniques are now enabling new hybrid CPU/FPGA computing resources to be integrated onto a single chip. While these new hybrids promise significant perfor...
David L. Andrews, Douglas Niehaus
ICIP
1995
IEEE
15 years 7 months ago
MFAST: a single chip highly parallel image processing architecture
Gerald G. Pechanek, M. Stojancic, Stamatis Vassili...
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IPPS
2006
IEEE
15 years 10 months ago
Early evaluation of the Cray XT3
Oak Ridge National Laboratory recently received delivery of a 5,294 processor Cray XT3. The XT3 is Cray’s third-generation massively parallel processing system. The system build...
Jeffrey S. Vetter, Sadaf R. Alam, Thomas H. Duniga...