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» Massively parallel processing on a chip
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112
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ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
15 years 6 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
101
Voted
MEMOCODE
2007
IEEE
15 years 6 months ago
Scheduling as Rule Composition
Bluespec is a high-level hardware description language used for architectural exploration, hardware modeling and synthesis of semiconductor chips. In Bluespec, one views hardware ...
Nirav Dave, Arvind, Michael Pellauer
CCECE
2006
IEEE
15 years 5 months ago
Packet CDMA Communication without Preambles
This paper applies a segmented matched filter for acquiring chip codephase alignment in direct-sequence CDMA packet communications. This alignment is essential for decoding the sp...
Md. Sajjad Rahaman, David E. Dodds
94
Voted
TCS
2008
14 years 11 months ago
Cleaning a network with brushes
Following the decontamination metaphor for searching a graph, we introduce a cleaning process, which is related to both the chip-firing game and edge searching. Brushes (instead o...
Margaret-Ellen Messinger, Richard J. Nowakowski, P...
112
Voted
ASPLOS
2012
ACM
13 years 7 months ago
Chameleon: operating system support for dynamic processors
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to para...
Sankaralingam Panneerselvam, Michael M. Swift