Sciweavers

39 search results - page 5 / 8
» Matrix Multiplication on Two Interconnected Processors
Sort
View
ARCS
2010
Springer
14 years 9 months ago
A Tightly Coupled Accelerator Infrastructure for Exact Arithmetics
Processor speed and available computing power constantly increases, enabling computation of more and more complex problems such as numerical simulations of physical processes. In t...
Fabian Nowak, Rainer Buchty
ET
2007
101views more  ET 2007»
14 years 9 months ago
Towards Nanoelectronics Processor Architectures
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliab...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
IEEEPACT
2005
IEEE
15 years 3 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
15 years 1 months ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
ARC
2012
Springer
280views Hardware» more  ARC 2012»
13 years 5 months ago
Scalable Memory Hierarchies for Embedded Manycore Systems
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
Sen Ma, Miaoqing Huang, Eugene Cartwright, David L...