26 search results - page 4 / 6 » Maximizing Performance by Retiming and Clock Skew Scheduling |
ISSS
1998
IEEE
15 years 1 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
ASPDAC
1999
ACM
15 years 1 months ago
1999
ACM
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring c...
ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
JPDC
2008
14 years 9 months ago
2008
Energy saving is becoming one of the major design issues in processor architectures with multiple functional units (FUs). Nested loops are usually the most critical part in multim...
SIPS
2006
IEEE
15 years 3 months ago
2006
IEEE
Abstract— This paper is interested in applying voltage overscaling (VOS) to reduce trellis decoder energy consumption, where the key issue is how to minimize the decoding perform...