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» Maximum Current Estimation in Programmable Logic Arrays
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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 1 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
CSB
2004
IEEE
108views Bioinformatics» more  CSB 2004»
15 years 1 months ago
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA
Our previous work to accelerate phylogeny inference using HW/SW(Hardware/Software) co-design has recently been extended to a more powerful embedded computing platform. In this pla...
Terrence S. T. Mak, Kai-Pui Lam
ARC
2009
Springer
134views Hardware» more  ARC 2009»
15 years 2 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
BMCBI
2006
115views more  BMCBI 2006»
14 years 9 months ago
SimArray: a user-friendly and user-configurable microarray design tool
Background: Microarrays were first developed to assess gene expression but are now also used to map protein-binding sites and to assess allelic variation between individuals. Rega...
Richard P. Auburn, Roslin R. Russell, Bettina Fisc...
ISCAS
2002
IEEE
141views Hardware» more  ISCAS 2002»
15 years 2 months ago
Power characterization of digital filters implemented on FPGA
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nann...