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» Maximum Current Estimation in Programmable Logic Arrays
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84
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GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
15 years 2 months ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...
ICCAD
2006
IEEE
149views Hardware» more  ICCAD 2006»
15 years 6 months ago
Thermal sensor allocation and placement for reconfigurable systems
Temperature monitoring using thermal sensors is an essential tool for evaluating the thermal behavior and sustaining the reliable operation in high-performance and high-power syst...
Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci...
IOLTS
2009
IEEE
231views Hardware» more  IOLTS 2009»
15 years 4 months ago
Designing fault tolerant FSM by nano-PLA
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault toleran...
Samary Baranov, Ilya Levin, Osnat Keren, Mark G. K...
ICSE
2011
IEEE-ACM
14 years 1 months ago
Inferring better contracts
Considerable progress has been made towards automatic support for one of the principal techniques available to enhance program reliability: equipping programs with extensive contr...
Yi Wei, Carlo A. Furia, Nikolay Kazmin, Bertrand M...
69
Voted
IPPS
2009
IEEE
15 years 4 months ago
Exploring FPGAs for accelerating the phylogenetic likelihood function
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological seq...
Nikolaos Alachiotis, Euripides Sotiriades, Apostol...