Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
We present a new tool, named DART, for automatically testing software that combines three main techniques: (1) automated extraction of the interface of a program with its external...
We consider the problem of finding "backbones" in multihop wireless networks. The backbone provides end-toend connectivity, allowing non-backbone nodes to save energy sin...
Seungjoon Lee, Bobby Bhattacharjee, Aravind Sriniv...
— Many architectures have been proposed to solve tightly-coupled multirobot tasks (MT) through coalitions of heterogeneous robots. However, several issues remain unaddressed. As ...