1362 search results - page 6 / 273 » Means, Correlations and Bounds |
ISVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
Formal verification has become an important step in circuit and system design. A prominent technique is Bounded Model Checking (BMC) which is widely used in industry. In BMC it i...
DATE
2003
IEEE
15 years 3 months ago
2003
IEEE
: Binary Decision Diagrams (BDDs) have been widely used in synthesis and verification. Boolean Satisfiability (SAT) Solvers, on the other hand, have been gaining
STOC
2003
ACM
15 years 2 months ago
2003
ACM
COCO
2008
Springer
14 years 11 months ago
2008
Springer
104
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CORR
2007
Springer
14 years 9 months ago
2007
Springer
Given multivariate time series, we study the problem of forming portfolios with maximum mean reversion while constraining the number of assets in these portfolios. We show that it...