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ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
15 years 4 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
ISLPED
2003
ACM
197views Hardware» more  ISLPED 2003»
15 years 4 months ago
Analyzing the energy consumption of security protocols
Security is critical to a wide range of wireless data applications and services. While several security mechanisms and protocols have been developed in the context of the wired In...
Nachiketh R. Potlapally, Srivaths Ravi, Anand Ragh...
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 4 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ISLPED
2003
ACM
152views Hardware» more  ISLPED 2003»
15 years 4 months ago
An MTCMOS design methodology and its application to mobile computing
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are use...
Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae P...
ISPD
2003
ACM
79views Hardware» more  ISPD 2003»
15 years 4 months ago
Floorplanning of pipelined array modules using sequence pairs
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
Matthew Moe, Herman Schmit
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