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ECRTS
2009
IEEE
14 years 7 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
ISCA
2011
IEEE
324views Hardware» more  ISCA 2011»
14 years 1 months ago
Prefetch-aware shared resource management for multi-core systems
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N....
ECRTS
2008
IEEE
15 years 4 months ago
Cache-Aware Real-Time Scheduling on Multicore Platforms: Heuristics and a Case Study
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
EUROPAR
2008
Springer
14 years 11 months ago
Parallel Lattice Boltzmann Flow Simulation on Emerging Multi-core Platforms
Abstract. A parallel Lattice Boltzmann Method (pLBM), which is based on hierarchical spatial decomposition, is designed to perform large-scale flow simulations. The algorithm uses ...
Liu Peng, Ken-ichi Nomura, Takehiro Oyakawa, Rajiv...
ICMCS
2009
IEEE
180views Multimedia» more  ICMCS 2009»
14 years 7 months ago
Foreground segmentation for static video via multi-core and multi-modal graph cut
We proposed a new foreground detection method using the static cameras. It merges multi-modality into graph cut energy function, and performs much better results than conventional...
Lun-Yu Chang, Winston H. Hsu