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MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
15 years 11 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
HOTI
2008
IEEE
15 years 11 months ago
Network Processing on an SPE Core in Cell Broadband Engine
Cell Broadband EngineTM is a multi-core system on a chip and is composed of a general-purpose Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs). Its ...
Yuji Kawamura, Takeshi Yamazaki, Hiroshi Kyusojin,...
ICPP
2008
IEEE
15 years 11 months ago
Enabling Streaming Remoting on Embedded Dual-Core Processors
Dual-core processors (and, to an extent, multicore processors) have been adopted in recent years to provide platforms that satisfy the performance requirements of popular multimed...
Kun-Yuan Hsieh, Yen-Chih Liu, Po-Wen Wu, Shou-Wei ...
ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
15 years 11 months ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
IEEEPACT
2007
IEEE
15 years 11 months ago
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Mo...