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» Measuring Operating System Overhead on CMT Processors
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ICS
2003
Tsinghua U.
15 years 6 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
SIGOPS
2010
179views more  SIGOPS 2010»
14 years 8 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
EUROSYS
2011
ACM
14 years 4 months ago
Database engines on multicores, why parallelize when you can distribute?
Multicore computers pose a substantial challenge to infrastructure software such as operating systems or databases. Such software typically evolves slower than the underlying hard...
Tudor-Ioan Salomie, Ionut Emanuel Subasu, Jana Gic...
VEE
2009
ACM
171views Virtualization» more  VEE 2009»
15 years 8 months ago
Dynamic memory balancing for virtual machines
Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying vi...
Weiming Zhao, Zhenlin Wang
LCTRTS
2009
Springer
15 years 8 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...