Sciweavers

402 search results - page 29 / 81
» Measuring Operating System Overhead on CMT Processors
Sort
View
TC
2010
14 years 8 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
CPAIOR
2006
Springer
15 years 5 months ago
Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs
Abstract. In this paper we introduce a complex allocation and scheduling problem for variable voltage Multi-Processor System-on-Chip (MPSoC) platforms. We propose a methodology to ...
Luca Benini, Davide Bertozzi, Alessio Guerri, Mich...
EWSN
2012
Springer
13 years 9 months ago
Low Power or High Performance? A Tradeoff Whose Time Has Come (and Nearly Gone)
Abstract. Some have argued that the dichotomy between high-performance operation and low resource utilization is false – an artifact that will soon succumb to Moore’s Law and c...
JeongGil Ko, Kevin Klues, Christian Richter, Wanja...
IWMM
2010
Springer
137views Hardware» more  IWMM 2010»
15 years 5 months ago
The locality of concurrent write barriers
Concurrent and incremental collectors require barriers to ensure correct synchronisation between mutator and collector. The overheads imposed by particular barriers on particular ...
Laurence Hellyer, Richard Jones, Antony L. Hosking
MICRO
2009
IEEE
120views Hardware» more  MICRO 2009»
15 years 8 months ago
Tribeca: design for PVT variations with local recovery and fine-grained adaptation
With continued advances in CMOS technology, parameter variations are emerging as a major design challenge. Irregularities during the fabrication of a microprocessor and variations...
Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, G...