Sciweavers

4396 search results - page 106 / 880
» Measuring the Architecture Design Process
Sort
View
DAC
2006
ACM
16 years 5 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
15 years 11 months ago
Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics
— Designers require variational information for robust designs. Characterization of such information can be costly for the novel nanoparticle interconnect process, which utilize ...
Rasit Onur Topaloglu
DAC
2002
ACM
16 years 5 months ago
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
16 years 4 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
16 years 4 months ago
Automatic Model Refinement for Fast Architecture Exploration
We present a methodology and algorithms for automatic refinement from a given design specification to an architecture model based on decisions in architecture exploration. An arch...
Junyu Peng, Samar Abdi, Daniel Gajski