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106
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ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
15 years 9 months ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
164
Voted
TC
2010
14 years 11 months ago
On the Problem of Evaluating the Performance of Multiprogrammed Workloads
Multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology defines whe...
Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Sa...
APPINF
2003
15 years 6 months ago
Comparing the Optimal Performance of Multiprocessor Architectures
Consider a parallel program with n processes and a synchronization granularity z. Consider also two multiprocessors: a multiprocessor with q processors and run-time reallocation o...
Lars Lundberg, Kamilla Klonowska, Magnus Broberg, ...
152
Voted
IEEEMM
2002
466views more  IEEEMM 2002»
15 years 4 months ago
Measuring Web Application Quality with WebQEM
measuring the product's "lower abstraction attributes."5 We see attributes as measurable properties of an entity--here, a Web application--and propose using a qualit...
Luis Olsina, Gustavo Rossi
PARELEC
2000
IEEE
15 years 8 months ago
Parallel Computing Environments and Methods
Recent advances in high-speed networks, rapid improvements in microprocessor design, and availability of highly performing clustering software implementations enables cost-effecti...
Ghassan Fadlallah, Michel Lavoie, Louis-A. Dessain...