4396 search results - page 120 / 880 » Measuring the Architecture Design Process |
148
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ISCA
2005
IEEE
15 years 10 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
118
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ICASSP
2011
IEEE
14 years 8 months ago
2011
IEEE
Current techniques used in pipelining recursive filters require significant hardware complexity. These techniques attempt to preserve the exact frequency response of the origina...
148
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ISLPED
2003
ACM
15 years 9 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
142
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ESTIMEDIA
2007
Springer
15 years 10 months ago
2007
Springer
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...
124
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ITCC
2003
IEEE
15 years 10 months ago
2003
IEEE
In this paper, we propose a software architecture model for the development of elaboration/transcoding modules for structured data. We define a flexible implementation approach ...