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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
15 years 11 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
DAC
2010
ACM
15 years 8 months ago
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
Lin Huang, Qiang Xu
DAC
2010
ACM
15 years 8 months ago
Cyber-physical energy systems: focus on smart buildings
Operating at the intersection of multiple sensing and control systems designed for occupant comfort, performability and operational efficiency, modern buildings represent a protot...
Jan Kleissl, Yuvraj Agarwal
133
Voted
DAC
2009
ACM
15 years 11 months ago
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation
It is unknown how to include stochastic process variation into fast-multipole-method (FMM) for a full chip capacitance extraction. This paper presents a parallel FMM extraction us...
Fang Gong, Hao Yu, Lei He
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
15 years 11 months ago
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...