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155
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VLSISP
2011
241views Database» more  VLSISP 2011»
14 years 12 months ago
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...
Gustavo A. Ruiz, Juan A. Michell
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 9 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
DAC
2003
ACM
16 years 6 months ago
A complexity effective communication model for behavioral modeling of signal processing applications
In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in beh...
M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S...
137
Voted
DATE
2008
IEEE
85views Hardware» more  DATE 2008»
15 years 11 months ago
Video Processing Requirements on SoC Infrastructures
Applications from the embedded consumer domain put challenging requirements on SoC infrastructures, i.e. interconnect and memory. Specifically, video applications demand large sto...
Pieter van der Wolf, Tomas Henriksson
CORR
2011
Springer
273views Education» more  CORR 2011»
14 years 12 months ago
Natural Language Processing (almost) from Scratch
We propose a unified neural network architecture and learning algorithm that can be applied to various natural language processing tasks including: part-of-speech tagging, chunki...
Ronan Collobert, Jason Weston, Léon Bottou,...