Sciweavers

4396 search results - page 638 / 880
» Measuring the Architecture Design Process
Sort
View
IPPS
2009
IEEE
16 years 28 days ago
A cross-input adaptive framework for GPU program optimizations
Abstract—Recent years have seen a trend in using graphic processing units (GPU) as accelerators for general-purpose computing. The inexpensive, single-chip, massively parallel ar...
Yixun Liu, Eddy Z. Zhang, Xipeng Shen
ISQED
2008
IEEE
154views Hardware» more  ISQED 2008»
16 years 20 days ago
Error Protected Data Bus Inversion Using Standard DRAM Components
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
Maurizio Skerlj, Paolo Ienne
FDL
2007
IEEE
16 years 18 days ago
Modelling Alternatives for Cycle Approximate Bus TLMs
Transaction level models (TLMs) can be constructed at t levels of abstraction, denoted as untimed (UT), cycle-approximate (CX), and cycle accurate (CA) in this paper. The choice o...
Martin Radetzki, Rauf Salimi Khaligh
ICC
2007
IEEE
145views Communications» more  ICC 2007»
16 years 18 days ago
Click on a Cluster: A Viable Approach to Scale Software-Based Routers
—Extensible software-based routers running on commodity off-the-shelf hardware and open-source operating systems have been motivated by the progress in hardware technologies and ...
Qinghua Ye, Mike H. MacGregor
ACSAC
2006
IEEE
16 years 10 days ago
Engineering Sufficiently Secure Computing
We propose an architecture of four complimentary technologies increasingly relevant to a growing number of home users and organizations: cryptography, separation kernels, formal v...
Brian Witten