4396 search results - page 661 / 880 » Measuring the Architecture Design Process |
129
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
This paper presents an optimal procrastinating voltage scheduling (OP-DVS) for hard real-time systems using stochastic workload information. Algorithms are presented for both sing...
118
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Antenna effect may damage gate oxides during plasma-based fabrication process. The antenna ratio of total exposed antenna area to total gate oxide area is directly related to the ...
170
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HPCA
2009
IEEE
16 years 6 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
150
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ICCAD
2001
IEEE
16 years 2 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
148
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MM
2009
ACM
16 years 17 days ago
2009
ACM
Programmable processors have great advantage over dedicated ASIC design under intense time-to-market pressure. However, realtime encoding of high-definition (HD) H.264 video (up t...