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IV
2007
IEEE
139views Visualization» more  IV 2007»
15 years 10 months ago
Investigating perceptual responses and shared understanding of architectural design ideas when communicated through different fo
Research to date has demonstrated the apparent differences how architects, as ‘experts’ and members of the public as ‘non-experts’ perceive and understand visual represent...
Nada Bates-Brkljac
CODES
2006
IEEE
15 years 10 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
DAC
2006
ACM
15 years 6 months ago
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
David Atienza, Pablo Garcia Del Valle, Giacomo Pac...
CODES
2006
IEEE
15 years 10 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
TVLSI
2008
133views more  TVLSI 2008»
15 years 4 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias