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ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
15 years 10 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
TAICPART
2006
IEEE
131views Education» more  TAICPART 2006»
15 years 10 months ago
Bogor: A Flexible Framework for Creating Software Model Checkers
Model checking has proven to be an effective technology for verification and debugging in hardware and more recently in software domains. With the proliferation of multicore arch...
Robby, Matthew B. Dwyer, John Hatcliff
ASSETS
2006
ACM
15 years 10 months ago
Improving non-visual web access using context
To browse the Web, blind people have to use screen readers, which process pages sequentially, making browsing timeconsuming. We present a prototype system, CSurf, which provides a...
Jalal Mahmud, Yevgen Borodin, Dipanjan Das, I. V. ...
JCDL
2006
ACM
140views Education» more  JCDL 2006»
15 years 10 months ago
Exploring erotics in Emily Dickinson's correspondence with text mining and visual interfaces
This paper describes a system to support humanities scholars in their interpretation of literary work. It presents a user interface and web architecture that integrates text minin...
Catherine Plaisant, James Rose, Bei Yu, Loretta Au...
MOBICOM
2006
ACM
15 years 10 months ago
Localization in underwater sensor networks: survey and challenges
In underwater sensor networks (UWSNs), determining the location of every sensor is important and the process of estimating the location of each node in a sensor network is known a...
Vijay R. Chandrasekhar, Winston Khoon Guan Seah, Y...