Sciweavers

8600 search results - page 435 / 1720
» Measuring with Timed Patterns
Sort
View
ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
15 years 9 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
IWANN
1999
Springer
15 years 9 months ago
Adaptive Resonance Theory Microchips
Recently, a real-time clustering microchip based on the ART1 algorithm has been reported. That chip was able to classify 100-bit input patterns into up to 18 categories. However, i...
Teresa Serrano-Gotarredona, Bernabé Linares...
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
15 years 6 months ago
Standard CMOS technology on-chip inductors with pn junctions substrate isolation
New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the re...
Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, M...
DKE
2008
108views more  DKE 2008»
15 years 4 months ago
The thematic and citation landscape of Data and Knowledge Engineering
The thematic and citation structures of Data and Knowledge Engineering (DKE) (1985-2007) are identified based on text analysis and citation analysis of the bibliographic records o...
Chaomei Chen, Il-Yeol Song, Xiaojun Yuan, Jian Zha...
ICDE
2008
IEEE
158views Database» more  ICDE 2008»
16 years 6 months ago
CARE: Finding Local Linear Correlations in High Dimensional Data
Finding latent patterns in high dimensional data is an important research problem with numerous applications. Existing approaches can be summarized into 3 categories: feature selec...
Xiang Zhang, Feng Pan, Wei Wang