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ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
14 years 7 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng
ASPDAC
2009
ACM
212views Hardware» more  ASPDAC 2009»
15 years 4 months ago
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
Kwangok Jeong, Andrew B. Kahng
FCT
2001
Springer
15 years 2 months ago
Polynomial Time Algorithms for Finding Unordered Tree Patterns with Internal Variables
Many documents such as Web documents or XML files have tree structures. A term tree is an unordered tree pattern consisting of internal variables and tree structures. In order to ...
Takayoshi Shoudai, Tomoyuki Uchida, Tetsuhiro Miya...
SDM
2009
SIAM
130views Data Mining» more  SDM 2009»
15 years 7 months ago
FuncICA for Time Series Pattern Discovery.
We introduce FuncICA, a new independent component analysis method for pattern discovery in inherently functional data, such as time series data. FuncICA can be considered an analo...
Alexander Gray, Nishant Mehta
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
15 years 1 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna