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» Mechanisms for Mapping High-Level Parallel Performance Data
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ICCD
2006
IEEE
139views Hardware» more  ICCD 2006»
15 years 10 months ago
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
Sean Leventhal, Manoj Franklin
CLOUD
2010
ACM
15 years 6 months ago
Stateful bulk processing for incremental analytics
This work addresses the need for stateful dataflow programs that can rapidly sift through huge, evolving data sets. These data-intensive applications perform complex multi-step c...
Dionysios Logothetis, Christopher Olston, Benjamin...
ISPDC
2008
IEEE
15 years 7 months ago
Load Balancing in Mesh-like Computations using Prediction Binary Trees
We present a load-balancing technique that exploits the temporal coherence, among successive computation phases, in mesh-like computations to be mapped on a cluster of processors....
Biagio Cosenza, Gennaro Cordasco, Rosario De Chiar...
IPPS
2002
IEEE
15 years 6 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
IEEEPACT
2000
IEEE
15 years 5 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier