Sciweavers

753 search results - page 119 / 151
» Mechanisms for Mapping High-Level Parallel Performance Data
Sort
View
EUROPAR
2010
Springer
15 years 1 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
AIPR
2008
IEEE
15 years 3 months ago
Low-cost, high-speed computer vision using NVIDIA's CUDA architecture
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
Seung In Park, Sean P. Ponce, Jing Huang, Yong Cao...
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
15 years 7 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...
GRID
2008
Springer
15 years 1 months ago
Cost and accuracy sensitive dynamic workflow composition over grid environments
A myriad of recent activities can be seen towards dynamic workflow composition for processing complex and data intensive problems. Meanwhile, the simultaneous emergence of the gri...
David Chiu, Sagar Deshpande, Gagan Agrawal, Rongxi...
ICDCSW
2005
IEEE
15 years 6 months ago
Adaptive Real-Time Anomaly Detection with Improved Index and Ability to Forget
Anomaly detection in IP networks, detection of deviations from what is considered normal, is an important complement to misuse detection based on known attack descriptions. Perfor...
Kalle Burbeck, Simin Nadjm-Tehrani