753 search results - page 123 / 151 » Mechanisms for Mapping High-Level Parallel Performance Data |
ISNN
2005
Springer
15 years 6 months ago
2005
Springer
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
137
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HOTI
2005
IEEE
15 years 6 months ago
2005
IEEE
Intrusion rule processing in reconfigurable hardware enables intrusion detection and prevention services to run at multi Gigabit/second rates. High-level intrusion rules mapped d...
113
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ICS
1997
Tsinghua U.
15 years 5 months ago
1997
Tsinghua U.
This paper makes the case for the use of XOR-based placement functions for cache memories. It shows that these XOR-mapping schemes can eliminate many conflict misses for direct-ma...
131
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BIBE
2007
IEEE
15 years 5 months ago
2007
IEEE
The computational power and memory bandwidth of graphics processing units (GPUs) have turned them into attractive platforms for general-purpose applications. In this paper, we expl...
136
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SIGCOMM
2012
ACM
13 years 3 months ago
2012
ACM
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case...