753 search results - page 130 / 151 » Mechanisms for Mapping High-Level Parallel Performance Data |
136
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INFOCOM
2011
IEEE
14 years 5 months ago
2011
IEEE
—In this paper we propose VIRO — a novel, virtual identifier (Id) routing paradigm for future networks. The objective is three-fold. First, VIRO directly addresses the challen...
150
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SIGMETRICS
2008
ACM
15 years 1 months ago
2008
ACM
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
ICPP
2009
IEEE
15 years 8 months ago
2009
IEEE
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
121
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HPCA
2002
IEEE
16 years 1 months ago
2002
IEEE
Clusters of high-end workstations and PCs are currently used in many application domains to perform large-scale computations or as scalable servers for I/O bound tasks. Although c...
107
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ICMCS
2006
IEEE
15 years 7 months ago
2006
IEEE
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...