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» Mechanisms for Mapping High-Level Parallel Performance Data
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ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
15 years 6 months ago
A case for FAME: FPGA architecture model execution
Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Mod...
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bi...
TOMACS
1998
140views more  TOMACS 1998»
15 years 25 days ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
15 years 6 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
BMCBI
2010
114views more  BMCBI 2010»
15 years 1 months ago
An integrative modular approach to systematically predict gene-phenotype associations
Background: Complex human diseases are often caused by multiple mutations, each of which contributes only a minor effect to the disease phenotype. To study the basis for these com...
Michael R. Mehan, Juan Nunez-Iglesias, Chao Dai, M...
BMCBI
2008
114views more  BMCBI 2008»
15 years 1 months ago
TiGER: A database for tissue-specific gene expression and regulation
Background: Understanding how genes are expressed and regulated in different tissues is a fundamental and challenging question. However, most of currently available biological dat...
Xiong Liu, Xueping Yu, Donald J. Zack, Heng Zhu, J...