753 search results - page 15 / 151 » Mechanisms for Mapping High-Level Parallel Performance Data |
89
Voted
CDES
2006
15 years 1 months ago
2006
- Many memory-sensitive embedded applications can tolerate small performance degradations if doing so can reduce the memory space requirements significantly. This paper explores th...
HPCA
2008
IEEE
16 years 1 days ago
2008
IEEE
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
ICCS
2007
Springer
15 years 5 months ago
2007
Springer
Abstract. The Southern California Earthquake Center initiated a major largescale earthquake simulation called TeraShake. The simulations propagated seismic waves across a domain of...
91
Voted
IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper we present MRI, a high level interface for selective monitoring of code regions and data structures in single and multiprocessor environments. MRI keeps transparent ...
112
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PADS
2003
ACM
15 years 5 months ago
2003
ACM
Wireless networks’ models differ from wired ones at least in the innovative dynamic effects of host-mobility and open-broadcast nature of the wireless medium. Topology changes d...